1. Field of Invention
The present invention relates to an apparatus for efficient testing of modules within integrated circuits. More particularly, the present invention provides an access scheme for efficient testing of standard modules within integrated circuits using previously developed module test vectors regardless of the configuration of the modules within the integrated circuit.
2. Description of the Prior Art
Integrated circuits find application today in many areas far afield of their original domain in the computer industry. They can be found in devices from dishwashers and microwave ovens to planes, medical equipment and communications devices. Because proper functioning of embedded integrated circuits is often critical to the device in which they operate, it is essential that comprehensive testing be performed when they are being mass produced to ensure that the end product performs as designed, and is as fault and error free as possible. Thus, because every chip must be tested during production, test overhead becomes a serious concern for semiconductor manufacturers.
Obviously, as chip designs become more complex, the physical overhead and time required for testing can contribute enormously to the overall cost of the devices. For simple chip designs it is a simple matter to test the chip as a whole. A set of test inputs, the test vectors, are developed, and if the chip is in good condition, expected outputs will result from passing those inputs into the device. However, as integrated circuits become more densely packed and complicated, the development of the input test vectors for testing the majority or the circuitry becomes very difficult to develop and expensive to implement for every chip design. Further, testing chips as a whole makes it difficult to isolate problems that may be recurring frequently in a given batch.
Today, integrated circuit design has taken on a modular approach in which there are certain modules that will be common within many integrated circuits, though they may be configured differently. For example, common modules include timers, counters, digital-to-analog converter, central processing units (CPU), direct memory access controllers (DMA), etc. Application Specific Integrated Circuits (ASIC) will usually be built around different configurations of the same modules. However, the configuration of the modules within a given chip will determine what test vectors are required to implement a chip-as-a-whole testing scheme. Thus, even though two chips may contain exactly the same modular elements, their unique configurations may require the development of completely different testing schemes. This is so because many of the modules will be embedded within the chip such that there is no direct access to them and their inputs will be signals which have propagated through other modules prior to reaching them. For example, in one configuration, to test a timer might require developing test vectors that will have to pass through a CPU on their way to the timer and then have to be propagated through a counter on their way out of the chip. In addition to the arduous task of simulating the chip to determine the desired inputs to get desired outputs, a bad response won't guarantee that the problem is within the timer. The problem may be occurring within a CPU or a counter or at any other point between the input pins and the output pins.
Obviously the problem is exacerbated when the number of modules within the integrated circuit increases and the level of module embeddedness becomes deeper. If it were possible to access each module directly then a standard set of test vectors for that type of module could be implemented. That is, every counter of a particular type would receive exactly the same test vectors as inputs, and exactly the same results would be expected. The problem is that rarely is every module directly accessible for both inputs and outputs. It requires a tremendous amount of silicon overhead to design complex integrated circuits such that all modules are directly accessible to system pins in that manner. Thus, there is a need for a design scheme which provides for accessing modules to deliver standard test vectors and a way to gather those modules' outputs, but without the overhead of trying to design integrated circuits with direct pin access to every module's inputs and outputs.